AMP I.10 – The Common Source Amplifier

Introduction

Just like bipolar junction transistors, we also have three classical amplifier configurations for JFET that lay the foundation for all JFET amplifier theory. They are the Common Source amplifier, the Common Drain amplifier, and the Common Gate amplifier. In this chapter we’ll discuss the Common Source amplifier.

JFET Particulars

Let’s recall the small signal equivalent circuit for our JFET:

Contrary to our BJT circuits, there is no current flowing into the gate: there is an open circuit after the gate. As we will see later, this will greatly increase our input resistance. Furthermore, no current flowing into the gate means that biasing is voltage only, and doesn’t consume power.

The Common Source Amplifier

The above schematic represents the common source amplifier: the input is applied at the gate, while the output is sampled at the drain. It is very similar to the common emitter amplifier, where input was applied at the base and output sampled at the collector. In this circuit, self-bias was used as the biasing method.

Just as we did for the BJT amplifier circuits, for each JFET configuration we will derive the voltage gain, current gain, input resistance, and output resistance.

Voltage Gain

Let’s draw our small signal equivalent circuit:

Remember that the current flowing through the Drain-Source junction is $I_D = g_m V_{GS}$ . It is important to note that our input voltage is not $V_{GS}$ , but only $V_G$ :

$v_{out} = V_{CC} - R_D I_D$
$v_{in} = v_G$

But, calculating the ration $\frac{v_{out}}{v_{in}}$ doesn’t give a meaningful answer. But what else do we know? Let’s take look more closely at $V_{GS}$ :

$v_{GS} = v_G - v_S = v_{in} - R_S I_D$

$v_{in} = v_{GS} + R_S I_D$

$v_{in} = v_{GS} + R_S g_m v_{GS}$

(1) $\begin{equation*} v_{in} = v_{GS} (1 + R_S g_m) \end{equation*}$

Now we’re getting somewhere! We can derive our voltage gain $A_v$ :

$\frac{v_{out}}{v_{in}} = \frac{V_{CC} - R_D I_D}{v_{GS} (1+R_S g_m)}$

$\frac{v_{out}}{v_{in}} = \frac{V_{CC} - R_D g_m v_{GS}}{v_{GS}(1+R_S g_m)}$

To get the gain, we simply differentiate this result:

$A_v = \frac{\Delta v_{out}}{\Delta v_{in}} = \frac{-R_D g_m v_{GS}}{v_{GS}(1+R_S g_m)} = -\frac{R_D g_m}{1 + R_S g_m}$

$A_v \approx - \frac{R_D}{R_S}$

The voltage is negative, so the common source amplifier is an inverting amplifier. However, the schematic I’ve shown you is not really a common source amplifier. Indeed, the source isn’t AC-grounded. Let’s change that and add a bypass capacitor on the source:

The small signal equivalent circuit is:

In which case, we have :

$v_{OUT} = V_{CC} - R_D I_D = V_{CC} - R_D g_m v_{GS}$
$v_{GS} = v_G - v_S = v_G$ (the source is AC grounded)

This gives us a voltage gain of $A_v = \frac{-R_D g_m v_{GS}}{v_{GS}} = -R_D g_m$ .

If we add a load $R_L$ to our circuit, this gain changes and becomes $A_v = -(R_D // R_L) gm$ .

Source Degeneration

So, we have a voltage gain. There is a small problem however: the gain is heavily dependent on $g_m$ , and in the case of JFETs, $g_m$ can vary widely from on transistor to the next. Just like the common emitter amplifier, we can reduce the effect of $g_m$ variability by introducing a source resistor: this is called source degeneration.

The small signal equivalent circuit is:

Let’s calculate the new voltage gain:

$v_{OUT} = V_{CC} - R_D I_D = V_{CC} - R_D g_m v_{GS}$
$v_{GS} = v_G - v_S = v_{IN} - R_{S1} I_D = v_{IN} - R_{S1} g_m v_{GS}$

We can express $v_{IN}$ as a function of $v_{GS}$ : $v_{IN} = v_{GS}(1+R_{S1}g_m)$

Now we can derive our voltage gain $A_v$ :

$A_v = \frac{\Delta v_{OUT}}{\Delta v_{IN}} = \frac{-R_D g_m v_{GS}}{v_{GS}(1 +R_{S1} g_m)} = -\frac{R_D g_m}{1 + R_{S1} g_m}$

$A_v \approx -\frac{R_D}{\frac{1}{g_m} + R_{S1}}$

To effectively use source degeneration, choose $R_{S1}$ high enough to swamp $\frac{1}{g_m}$ , but not too large as to kill the gain. Doing so, we can ignore $\frac{1}{g_m}$ and the gain will be approximately $-\frac{R_D}{R_{S1}}$ .

Current Gain

As we saw earlier, there is no current flowing through the gate of our JFET. This means that no current from our input signal can flow into our amplifier. This circuit draws no current, but still delivers current. The current gain is infinite.

Input Resistance

There is an open circuit at the gate. The only path the input signal can take is through $R_G$ . Technically, $R_G$ isn’t required, but it is good practice to include it. This way, if something goes wrong with your input signal (ground problems, etc), there is a path to ground for the gate, allowing the transistor to fully ‘deactivate’ and avoid damage. In the absence of an input signal, the gate is grounded and not floating.

Back to our input resistance. Following the above circuit, it is trivially $R_{in} = R_G$ . We choose $R_G$ to be generally in the hundreds of k $\Omega$ or in the megaohm range.

We see here one big advantage of JFET’s over BJTs: they have incredibly high input resistances. If we are using voltage dividers for biasing the gate, since there is no biasing current, there is no need for a stiff voltage source: you can use very high value resistors and greatly reduce the current draw of your biasing network.

$R_{in} \approx M\Omega$

Output Resistance

To calculate the output resistance the academic way, we need to ground the input, and apply a test signal at the output $v_{test}$ , and calculate the ratio $\frac{v_{test}}{i_{test}}$ .

$i_{test} = \frac{v_{test}}{R_D} + g_m v_{GS}$

Lets explicit $v_{GS}$ :

$v_{GS} = v_G - V_S$

However, we know the input is grounded, so $v_G = 0$ , and the source is also AC-grounded by the bypass capacitor. This gives us $v_S = 0$ , and thus $v_{GS} = 0$ . The output resistance is then simply: